We are looking for experienced Senior IP/SOC verification Engineers for our Interface IP Verification team in Bangalore. Does this sound like a good role for you?

- Senior Staff/Principal IP/SOC Verification Engineers (Interface-IP)
- Experience : 9years & above
- Location: Bengaluru
- Bachelors in Electronics Engineering with 9years of experience, or Master's in Electronics Engineering with 8years of hands-on ASIC or SoC verification experience
- Deep expertise in System Verilog and UVM methodology, with a track record of building scalable verification environments from the ground up
- Solid protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements
- Proven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff
- Solid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim
- Experience with verification IP development, assertion-based verification, or formal methods is a strong plus
- Knowledge of modern SoC architectures and high-speed communication interfaces is a plus
- Job responsibilities:
- Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff
- Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations




- Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios
- Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality
- Debug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators
- Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle
- Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices

The Team You’ll Be A Part Of: You will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.

Please share your updated CV to [email protected] or refer who would like to explore this opportunity.

- Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

📌 Senior ASIC Verification Engineers (Bengaluru)
🏢 Synopsys
📍 Bengaluru