Hiring Alert | RTL Design | Bangalore/Hyderabad
- JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions.
- Responsible for linting and simulation of design. Work with synthesis and backend teams for physical
- Strong background in RTL design using Verilog/VHDL.
- Timing Constraints (SDC) & Static Timing Analysis .
- Strong understanding and usage of ASIC and/or FPGA software tool chain like Vivado or Quartus.
- Solid Digital Design Fundamentals and applications
TCL Scripting language. Scripting language like Tcl, Perl or Python
Qualifications
- BS or MS in EE or CE with 2+ to 8+ years of experience in digital design and/or timing closure.
? Interested candidates can share their updated resume at:
[email protected]
Regards,
Jaya
📌 Opening for RTL Design Engineer - Bangalore/Hyderabad (Bengaluru)
🏢 UST
📍 Bengaluru