Opening for Design Verification - Bangalore / Hyderabad
: -
System Verilog based UVM Functional verification, Behavioral modelling of functional blocks.
System level performance verification, traffic patterns, bandwidth & latency analysis.
Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol.
Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.
Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
Basic Job Deliverable: -
Setup verification workplace and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera
SV/UVM Functional verification
Expertise in Vivado for simulation debugs
? Interested candidates can share their updated resumes
[email protected] or DM me for more details.
Regards,
Jaya
📌 Opening for Design Verification - Bangalore / Hyderabad (Bengaluru)
🏢 UST
📍 Bengaluru