14 Nov
|
Creeno Solutions Private
|
India
14 Nov
Creeno Solutions Private
India
Physical Design
RTL to GDS including, Synthesis + PNR
Fusion compiler / Cadence flow (Innovus)
Good understanding Macro placement, Floor planning, placement CTS, Routing
Design planning (partitioning, bump planning & Routing)
Very valuable understanding of STA
Very good Debugging skill
Handling at least 10 member team and driving project
Understanding about Analog block integration
Power grid creation
Low power design
Signoff checks
LEC ( conformal)
RV (ansys)
LV (drc clean up ‿ caliber)
PTPX
VCLP (vc static checks)
Timing closure (PT ECO/ Tweaker)
ESD runs
📌 Physical Design (India)
🏢 Creeno Solutions Private
📍 India