Job Description
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
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Bangalore /Hyderabad/Kochi
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Job Description: Full Chip RTL Design Architect
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We are seeking a highly skilled and experienced Full Chip RTL Design Architect to join our agile team. This role requires a deep understanding of RTL (Register-Transfer Level) design, SoC (System-on-Chip) architecture, and a passion for innovation in semiconductor design. The ideal candidate will play a critical role in defining and implementing full chip-level RTL designs and ensuring their successful execution.
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Key Responsibilities
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1. RTL Architecture and Design:
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- Define and develop full chip architecture and RTL designs for complex SoCs.
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- Drive the top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency.
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- Collaborate on micro-architectural specifications and ensure seamless implementation.
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2. Design Methodology and Implementation:
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- Develop and optimize RTL design methodologies to improve quality, performance, and power efficiency.
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- Lead RTL design reviews and provide technical guidance to design teams.
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- Ensure compliance with coding standards, quality metrics, and verification requirements.
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3. Cross-Functional Collaboration:
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- Work closely with system architects, verification engineers, physical design teams, and software developers to align design specifications and deliverables.
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- Provide feedback and solutions to cross-functional teams to resolve design challenges at all levels of the chip hierarchy.
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4. Technical Leadership:
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- Mentor and guide junior RTL engineers and team members, fostering a culture of technical excellence.
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- Stay updated with advancements in RTL design tools, methodologies, and technologies to improve design practices.
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5. Verification and Validation:
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- Support pre-silicon verification efforts and collaborate with verification engineers to develop comprehensive test plans.
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- Analyze simulation results, debug issues, and ensure that the design meets all functional, timing, and power requirements.
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6. Performance Optimization:
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- Identify and resolve bottlenecks in design performance, power, and area (PPA).
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- Perform trade-off analysis and optimize designs for efficiency at the system level.
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Required Qualifications
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- Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
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- Experience:
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- 15+ years of experience in RTL design, SoC architecture, and integration.
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- Proven experience in full chip-level design for complex SoCs.
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- Technical Expertise:
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- In-depth knowledge of RTL design languages such as Verilog and SystemVerilog.
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- Experience with low-power design techniques and power optimization.
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- Expertise in debugging tools, synthesis, timing analysis, and simulation.
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- Familiarity with design-for-test (DFT), design-for-debug (DFD), and physical design constraints.
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- Problem-Solving Skills:
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- Strong analytical and debugging skills, with the ability to resolve complex technical issues.
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- Communication Skills:
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- Excellent verbal and written communication skills, with the ability to collaborate effectively across teams.
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Preferred Qualifications
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- Advanced Degree: A Master's or Ph.D. in Electrical or Computer Engineering.
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- Certifications: Relevant certifications in SoC architecture or design tools.
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- Tool Proficiency:
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- Familiarity with tools like Synopsys, Cadence, or Mentor Graphics for RTL and synthesis.
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- Experience with high-level synthesis (HLS) tools is a plus.
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- Industry Knowledge: Experience with the latest industry trends in AI, automotive SoCs, or 5G systems.
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Skills
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SoC
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Architecture
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AO
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Automotive
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5G
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Verilog
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Systemverilog
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PPA
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Contact
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Uday
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[email protected]
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Mulya Technologies
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"Mining the Knowledge Community"
📌 Full Chip RTL Design Architect (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru