Senior Memory Design Engineer

Location: Bengaluru

Experience: 5–10 Years

Job Type: Full-time

Role Overview

We are looking for a Senior Memory Design Engineer to drive circuit-level design and optimization of advanced memory macros. The role requires strong expertise in SRAM/Memory circuit design, custom transistor-level design, simulation, characterization, and PVT analysis.

Key Responsibilities

- Design and develop SRAM/Memory macros at transistor and circuit level. - Work on bitcell, sense amplifier, precharge, write driver, decoder, and peripheral circuits. - Perform schematic design, transistor sizing, simulations, and circuit optimization. - Analyze PVT, Monte Carlo, mismatch, variation, leakage, power, and performance. - Drive memory timing, power, stability, and reliability characterization. - Debug circuit-level issues and improve PPA and yield. - Collaborate with Layout, STA, Verification, and Silicon teams for memory macro development and signoff. - Support silicon correlation, characterization, and post-silicon debug.

Core Technical Skills





- Robust hands-on experience in SRAM / Memory circuit design. - Expertise in Cadence Virtuoso and transistor-level simulation. - Strong understanding of CMOS fundamentals, device physics, and circuit analysis. - Experience with SPICE simulations, PVT corners, Monte Carlo, and statistical analysis. - Knowledge of memory timing, stability, leakage, power, and yield optimization. - Exposure to advanced technology nodes and low-voltage memory design is a plus. - Strong scripting/debugging skills using Python/Perl/Tcl is desirable.

Qualifications

- B.E./B.Tech/M.E./M.Tech in Electrical/Electronics/VLSI or related discipline. - 5–10 years of relevant industry experience in Memory Design / Custom Circuit Design.

Preferred: Candidates with end-to-end ownership of memory macros from architecture → circuit design → simulation → characterization → silicon correlation.

📌 Senior Memory Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru