Job DescriptionHi All,

NGreetings from Eximietas Design...!

NEximietas Hiring Principal SoC DFT Engineers | Bengaluru Location.

NExperience: Min 10+Years.

NLocations:- Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.

NSan Jose (Bay Area), USA

N

n
- Eligibility (USA): U.S. Permanent Residents (Green Card holders).
N

nJob Description:

NWe are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether

Nyou are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles

Nthat will challenge and grow your skills in advanced silicon testing.

NYou will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across

Ncomplex IP, subsystem, and SOC designs.

NCore Responsibilities:

NEnd-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.

NScan architecture definition and implementation at RTL and gate level, including EDT and

NOCC.

nExecution of block-level ATPG, DRC analysis, and coverage optimization.

NHandling of pattern simulations, including both timing and non-timing simulations.

NSOC-level integration, including pattern retargeting to subsystem and full-chip levels.

NIntegration, simulation,and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).

NIndependent debugging ofDFT simulations and netlist-related issues.

NClose collaboration withdesign, verification, and physical design teams to ensure DFT

Nreadiness.

nOwnership of DFT sign-off activities and deliverables.

NKey Responsibilities:

NDevelop and implement robust DFT architectures for IP, subsystem, and SOC designs.

NPerform scan insertion, ATPG generation,



and pattern validation at block and top levels.

NAnalyze and resolve coverage, DRC, and simulation failures to meet quality targets.

NDefine and execute DFT strategies aligned with project requirements and schedules.

NSupport pre-silicon and post-silicon test requirements.

NServe as the DFT point of contact for assigned projects, responsible for verification and test

Nreadiness sign-off.

nTechnical Requirements:

NMust-Have Skills:

NStrong experience in netlist handling and ATPG simulations.

NProven expertise in block-level and SOC-level pattern retargeting and debugging.

NIn-depth understanding of ICL and PDL standards.

NHands-on experience withat least one major DFT tool suite:

No Siemens Tessent

no Synopsys TestMAX / TetraMAX

No Cadence Modus

nPreferred & Advanced Skills:

NExperience with Streaming Scan Network (SSN).

NKnowledge of Analog and Mixed-Signal DFT methodologies.

NProficiency with SpyGlass for DFT linting and early-stage analysis.

NExposure to RTL-level DFT insertion and validation.

NStrong scripting skills (TCL, Python, Perl) for automation.

NWhat We Offer:

N

n
- Prospect to work on cutting-edge semiconductor designs and innovative technologies.
N
- Collaborative and inclusive work environment.
N
- Competitive compensation and benefits package.
N
- Professional growth anddevelopment opportunities.
N

nIf this opportunity interests you—or if you know someone suitable—please send your updated resume to: [email protected].

NReferrals are highly appreciated.

NBest regards,

nMaruthy Prasaad

NAssociate VLSI Manager - Talent Acquisition | Visakhapatnam

NEximietas Design

[email protected]

N+91 (phone hidden).

📌 Principal Soc Dft Engineer_bengaluru (Bengaluru)
🏢 Eximietas Design
📍 Bengaluru