Job DescriptionJob Summary

NWe are looking for a skilled Physical Design Engineer to support end-to-end ASIC/SoC implementation from netlist/RTL to GDSII. The engineer will be responsible for physical implementation, timing closure, PPA optimization, physical verification, and sign-off while working closely with RTL, synthesis, STA, DFT, and verification teams.

NKey Responsibilities

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- Execute the complete physical design flow:
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- Floorplanning
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- Power planning
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- Placement
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- Clock Tree Synthesis (CTS)
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- Routing
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- Optimization
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- ECO implementation
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- Physical sign-off
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- Perform Static Timing Analysis (STA) and resolve setup, hold, transition, and clock violations.
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- Analyze and optimize timing, power, area, congestion, and signal integrity.
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- Work on MMMC (Multi-Mode Multi-Corner) implementation and timing closure.
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- Develop and review timing constraints, including SDC, clocks, generated clocks, and timing exceptions.
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- Perform physical verification and sign-off activities including DRC, LVS, antenna, EM/IR, and power integrity checks.
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- Debug placement, routing, congestion, timing, and physical-design violations.
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- Collaborate with RTL, synthesis, STA, DFT, power, and verification teams to achieve project milestones.
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- Support tape-out activities and ensure design quality meets performance, power, area, and reliability targets.
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- Develop and improve implementation flows using Tcl/Python/Perl/Shell scripting.
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- Participate in methodology development and automation initiatives.
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nRequired TechnicalSkills

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- Robust understanding of ASIC/VLSI Physical Design flow from RTL/Netlist to GDSII.
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- Good knowledge of:
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- Floorplanning
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- Placement
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- CTS
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- Routing
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- Timing closure
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- ECO
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- Physical verification
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- Power planning
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- Strong understanding of setup/hold timing and STA.
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- Knowledge of MMMC analysis and timing constraints.
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- Experience with industry-standard EDA tools such as:
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- Cadence Innovus
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- Synopsys ICC2/Fusion Compiler
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- Synopsys PrimeTime
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- Cadence Tempus
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- Calibre/ICV
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- Scripting knowledge in Tcl, Python, Perl, or Shell.
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- Understanding of DRC, LVS, EM/IR and power integrity is preferred.
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- Exposure to low-power design/UPF and advanced technology nodes is an advantage.
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nEducation

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- B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, Microelectronics, or a related field.
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nExperience

n3–6 years: Physical Design Engineer

📌 Pd Engineer-Noida (Faridabad)
🏢 Mirafra Technologies
📍 Faridabad