Hiring: Memory Layout Engineers /n Experience: 2–6 Years /n Locations: Bangalore | Noida | Hyderabad /n Notice Period: Immediate Joiners / Short Notice Preferred /n /n Key Responsibilities: /n /n

- Hands-on experience in Memory Layout / Custom Layout for SRAM, ROM, NVM or Memory Compiler blocks.

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- Experience in Bitcell, Memory Array, Row/Column Decoder, Sense Amplifier, I/O and Peripheral layouts.

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- Strong knowledge of Floorplanning, Routing, Hierarchical Layout & Layout Optimization .

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- Hands-on experience with DRC, LVS, ERC, Antenna, EM/IR and Physical Verification .

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- Positive understanding of CMOS/FinFET technologies, layout rules, matching, parasitics and PPA optimization .

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- Proficiency in Cadence Virtuoso/Virtuoso XL and preferably Calibre .

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- Knowledge of Memory Compiler / Tiling / Automation is an added advantage.

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- Exposure to SKILL / Perl / TCL / Shell scripting is a plus.

/n /n Education: BE/B.Tech/M.Tech in ECE, EE, VLSI, Microelectronics or related field. /n Ideal Candidate: Memory/Custom Layout Engineer with strong hands-on implementation and physical verification experience. Current industry postings similarly emphasize Virtuoso, DRC/LVS, memory arrays and physical verification. /n /n Interested candidates can share their updated CV with: /n Total Experience | Relevant Memory Layout Experience | Current Location | Notice Period | Preferred Location /n

📌 Memory Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru