Lead Synthesis Engineer /n Location: Bengaluru, India /n Experience: 6–12 Years /n About the Role /n We're looking for a Lead Synthesis Engineer to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. You'll own synthesis convergence, optimize PPA, and collaborate with RTL, STA, DFT, and Physical Design teams to deliver high-quality silicon. /n What You'll Do /n /n

- Drive RTL synthesis using Synopsys Design Compiler/Fusion Compiler.

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- Optimize designs for Power, Performance, and Area (PPA) while meeting timing and design constraints.

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- Develop and debug SDC constraints, synthesis scripts, and automation flows.

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- Analyze timing, area, power, and QoR reports; resolve synthesis and logical issues.

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- Work closely with RTL, STA, DFT, Physical Design, and ECO teams to achieve implementation closure.

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- Support low-power methodologies, LEC, and synthesis signoff across advanced process nodes.

/n /n What We're Looking For /n /n

- 6–12 years of experience in ASIC/SoC Synthesis.

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- Strong expertise in Synopsys Design Compiler, Fusion Compiler, TCL scripting, and SDC.

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- Solid understanding of timing constraints, clock gating, UPF, low-power design, LEC, and ECO flows.

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- Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.

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- Robust debugging, problem-solving, and cross-functional collaboration skills.

/n /n Build next-generation silicon by delivering world-class synthesis quality across cutting-edge SoCs.

📌 Lead Synthesis Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru