Mirafra Technologies is Hiring Design Verification Engineer

Experience: 3–5 Years

Role: Design Verification (DV) Engineer

Availability - 0 to 30 days

Key Responsibilities

- Develop and maintain SystemVerilog/UVM-based verification environments for IP and subsystem-level verification.
- Create and execute verification test plans aligned with design specifications.
- Perform constrained-random and directed testing.
- Implement and drive functional and code coverage closure.
- Debug complex RTL and testbench failures using waveform analysis and industry-standard tools.
- Collaborate with Architecture, RTL Design, and Validation teams.
- Support SoC-level verification and IP integration when required.
- Manage regressions, failure triage, and testbench optimization.
- Prepare verification reports, documentation, and status updates.

Required Skills




- 3–5 years of experience in Digital Design Verification
- Strong hands-on experience in:

- SystemVerilog

- UVM

- UVM Testbench Development
- Constrained-Random Verification
- Coverage-Driven Verification

- Robust understanding of

- Digital Logic Design

- State Machines

- Synchronous Design Principles
- Excellent debugging and root-cause analysis skills.
- Experience with functional/code coverage closure and verification sign-off.

Qualification Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.

Location: Hyderabad

Interested candidates: Share your updated resume at [email protected]

📌 Hiring 3+ Verification Engineers -Mirafra Technologies HYD (Hyderabad)
🏢 Mirafra
📍 Hyderabad