RTL & FPGA Design Engineer /n Experience : 4-6 years /n Location : Hyderabad /n /n /n Core Skills: RTL Digital Design (Verilog/VHDL), Vivado toolchain (Design creation to Bitstream generation), and timing/IO constraints. /n Architecture & Interfaces: Strong grasp of AXI/AHB/CHI/ACE5 buses, peripherals (USB, Ethernet), and Video IPs (ISP/Encoder/Decoder). /n Debugging & Tools: Industry-standard front-end waveform debugging, ILA, Unix setting, and scripting (Tcl/Python/Perl). /n Bonus: Hands-on experience with pre-silicon platforms and automated verification flows. /n /n ? Interested candidates, please send your resume to
[email protected]!
📌 RTL - FPGA Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad