Hi All, /n Greetings from Eximietas Design...! /n Eximietas Hiring Principal SoC DFT Engineers | Bengaluru Location. /n Experience: Min 10+Years. /n Locations:

- Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam. /n San Jose (Bay Area), USA /n /n
- Eligibility (USA): U.S.

Permanent

Residents (Green Card holders).

/n /n : /n We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether /n you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles /n that will challenge and grow your skills in advanced silicon testing. /n You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across /n complex IP, subsystem, and SOC designs. /n Core Responsibilities: /n  End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off. /n  Scan architecture definition and implementation at RTL and gate level, including EDT and /n OCC. /n  Execution of block-level ATPG, DRC analysis, and coverage optimization. /n  Handling of pattern simulations, including both timing and non-timing simulations. /n  SOC-level integration, including pattern retargeting to subsystem and full-chip levels. /n  Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG). /n  Independent debugging of DFT simulations and netlist-related issues. /n  Close collaboration with design, verification, and physical design teams to ensure DFT /n readiness. /n  Ownership of DFT sign-off activities and deliverables. /n Key Responsibilities: /n  Develop and implement robust DFT architectures for IP, subsystem, and SOC designs. /n  Perform scan insertion, ATPG generation, and pattern validation at block and top levels.



/n  Analyze and resolve coverage, DRC, and simulation failures to meet quality targets. /n  Define and execute DFT strategies aligned with project requirements and schedules. /n  Support pre-silicon and post-silicon test requirements. /n  Serve as the DFT point of contact for assigned projects, responsible for verification and test /n readiness sign-off. /n Technical Requirements: /n Must-Have Skills: /n  Strong experience in netlist handling and ATPG simulations. /n  Proven expertise in block-level and SOC-level pattern retargeting and debugging. /n  In-depth understanding of ICL and PDL standards. /n  Hands-on experience with at least one major DFT tool suite: /n o Siemens Tessent /n o Synopsys TestMAX / TetraMAX /n o Cadence Modus /n Preferred & Advanced Skills: /n  Experience with Streaming Scan Network (SSN). /n  Knowledge of Analog and Mixed-Signal DFT methodologies. /n  Proficiency with SpyGlass for DFT linting and early-stage analysis. /n  Exposure to RTL-level DFT insertion and validation. /n  Strong scripting skills (TCL, Python, Perl) for automation. /n What We Offer: /n /n

- Opportunity to work on cutting-edge semiconductor designs and innovative technologies.

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- Collaborative and inclusive work environment.

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- Competitive compensation and benefits package.

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- Skilled growth and development opportunities.

/n /n If this opportunity interests you—or if you know someone suitable—please send your updated resume to: [email protected]. /n Referrals are highly appreciated. /n Best regards, /n Maruthy Prasaad /n Associate VLSI Manager - Talent Acquisition | Visakhapatnam /n Eximietas Design /n [email protected] /n +91 (phone hidden).

📌 Principal SoC DFT Engineer_Bengaluru (Bengaluru)
🏢 Eximietas Design
📍 Bengaluru