Responsibilities

n

n
- As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr. DFT Engineers.
n
- Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.
n
- Create test vectors or oversee their creation.
n
- Collaborate with physical design team to close timing in DFT mode.
n
- Sign-off DFT requirements are being met.
n
- Work with testing team to bring-up test patterns on silicon.
n

n

nRequirements

n

n
- Minimum Qualifications
n
- BE/MS degree in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.
n




- Hands-on expertise with Mentor/Synopsys test generation tools for large complex designs.
n
- DFT lead experience for complex SOC TO and Production.
n
- Robust fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST, SSN.
n

n

nPreferred Qualifications

n

n
- Experience with synthesis, STA and back-end implementation flows.
n
- Familiar with Tessent shell flow for DFT instruments insertion include MBIST, IJTAG, SSN, BSCAN, OCC etc.
n
- Solid Lab and test floor bring-up and debug experience.
n
- Yield estimation and test optimization.
n
- DFT AI mindset.
n

n

nMore information about NXP in India...

📌 Principal DFT Engineers (Pune)
🏢 NXP Semiconductors
📍 Pune