Senior Analog Layout Engineer /n /n Location: Hyderabad, Bangalore /n Experience: 4 to 6 Years /n Notice Period: Immediate /n /n : /n Key Responsibilities /n /n

- Custom Layout Design: Lead the layout development of critical analog blocks, including high-speed ADCs/DACs, PLLs, SerDes, Bandgaps, and LDOs.

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- Advanced Node Implementation: Navigate challenges unique to sub-3nm nodes, such as multi-patterning, EUV constraints, and FinFET/GAAFET-specific layout-dependent effects (LDE).

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- Physical Verification: Execute and debug comprehensive verification flows, including DRC, LVS, ERC, Antenna, and Latch-up checks using industry-standard tools.

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- Extraction & Analysis: Perform parasitic extraction (PEX) and collaborate with designers on post-layout simulations to meet stringent timing and performance targets.

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- Floorplanning: Optimize block-level and top-level floorplans to manage IR drop, Electromigration (EM), and Thermal-aware placement.

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- Reliability & DFM: Implement Design for Manufacturability (DFM) guidelines and ensure robust ESD/latch-up protection strategies.





/n /n Technical Skills & Qualifications /n /n

- Education: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or Electrical Engineering.

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- EDA Tools: Expert proficiency in Cadence Virtuoso (VXL/GXL) and Mentor Graphics Calibre (DRC/LVS/PEX).

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- Process Experience: Proven track record with FinFET technologies (7nm, 5nm) and direct exposure to 3nm or below nodes.

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- Analog Fundamentals: Deep understanding of matching techniques (Common Centroid, Interdigitation), shielding, and isolation (Deep N-Well, Guard Rings).

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- Scripting (Preferred): Familiarity with SKILL, Perl, or Tcl for layout automation and productivity enhancement.

/n /n Soft Skills /n /n

- Solid problem-solving skills for debugging complex verification errors.

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- Ability to mentor junior engineers and lead small-scale block integrations.

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- Excellent communication skills for collaborating with global cross-functional teams.

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📌 Analog Layout (Hyderabad)
🏢 ACL Digital
📍 Hyderabad