Job Description

Primary purpose of the role

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The role involves taking existing FPGA design documentation, signal-mapping sheets and Proto-1 hardware from partially drafted specifications through to a working, timing-clean and system-validated FPGA implementation . The position will develop high-speed data-processing pipelines, interface with ADCs, DACs and communication peripherals, implement robust clock-domain and reset architectures, and collaborate closely with Hardware, Embedded Software and Application teams.

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This is a hands-on individual contributor role requiring solid expertise in VHDL, AMD Xilinx FPGA architecture, Vivado, high-speed data acquisition, timing closure, CDC, LVDS interfaces and hardware debugging.

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Major responsibilities:

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RTL Design & FPGA Implementation

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Clocking, CDC & Reset Architecture

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High-Speed LVDS & Data Capture

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Timing Closure & FPGA Optimisation

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Verification & Validation

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Hardware Bring-Up & Debugging

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FPGA Configuration & Release Management

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Cross-Functional Collaboration

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Documentation & Design Governance

📌 Field Programmable Gate Arrays Engineer Mumbai (India)
🏢 Metal Power Analytical
📍 India