Job Description

Senior Memory Design Engineer

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Location: Bengaluru

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Experience: 5–10 Years

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Job Type: Full-time

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Role Overview

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We are looking for a Senior Memory Design Engineer to drive circuit-level design and optimization of advanced memory macros. The role requires robust expertise in SRAM/Memory circuit design, custom transistor-level design, simulation, characterization, and PVT analysis.

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Key Responsibilities

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Design and develop SRAM/Memory macros at transistor and circuit level.
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Work on bitcell, sense amplifier, precharge, write driver, decoder, and peripheral circuits.
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Perform schematic design, transistor sizing, simulations, and circuit optimization.
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Analyze PVT, Monte Carlo, mismatch, variation, leakage, power, and performance.
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Drive memory timing, power, stability, and reliability characterization.
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Debug circuit-level issues and improve PPA and yield.
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Collaborate with Layout, STA, Verification, and Silicon teams for memory macro development and signoff.
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Support silicon correlation, characterization, and post-silicon debug.
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Core Technical Skills

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Strong hands-on experience in SRAM / Memory circuit design.
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Expertise in Cadence Virtuoso and transistor-level simulation.
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Robust understanding of CMOS fundamentals, device physics, and circuit analysis.
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Experience with SPICE simulations, PVT corners, Monte Carlo, and statistical analysis.
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Knowledge of memory timing, stability, leakage, power, and yield optimization.
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Exposure to advanced technology nodes and low-voltage memory design is a plus.
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Solid scripting/debugging skills using Python/Perl/Tcl is desirable.
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Qualifications

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B.E./B.Tech/M.E./M.Tech in Electrical/Electronics/VLSI or related discipline.
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5–10 years of relevant industry experience in Memory Design / Custom Circuit Design.
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Preferred: Candidates with end-to-end ownership of memory macros from architecture → circuit design → simulation → characterization → silicon correlation.

📌 Senior Memory Design Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru