SmartSOC Solutions is dedicated to delivering cutting-edge semiconductor solutions. Our mission is to innovate and excel in the field of advanced technology, fostering a culture of collaboration and excellence.
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Qualifications
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4 to 12 years of relevant experience in Analog Layout Design.
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Mandatory: Hands-on experience with FinFET technology or Samsung Foundry process technologies.
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Robust experience in advanced technology nodes such as 2nm, 3nm, 5nm, or 7nm.
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Experience in custom analog layout, DRC/LVS/ERC/PEX closure, and layout optimization.
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Immediate joiners or candidates who can join within a short notice period are preferred.
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Responsibilities:
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Develop high-quality full-custom analog and mixed-signal layouts.
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Perform floorplanning, device matching, routing,
shielding, and optimization for analog circuits.
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Execute layout verification including DRC, LVS, ERC, and PEX closure.
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Ensure layout quality while meeting performance, power, area, and reliability requirements.
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Collaborate with circuit designers to resolve layout-related issues and optimize design performance.
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Work with advanced process technologies including FinFET nodes (2nm, 3nm, 5nm, and 7nm).
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Perform parasitic-aware layout optimization and support post-layout verification.
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Ensure compliance with foundry design rules and best layout practices.
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Participate in design reviews and contribute to silicon bring-up support when required.
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