Job Description:
5 to 8 years of experience in RTL Synthesis, Timing Constraints / SDC checking / reviewing / small fixes / finding errors etc.
Should have done at least 3 ASIC projects.
CDC, Lint clean up and automation with scripts, TCL, Perl Scripting.
Timing Report analysis, Static Timing Analysis
Formal Verification familiarity
UPF / Low Power Design is a plus.
Tools :
Genus / FC : Synthesis, Optimization or DC compiler, DCTopo
Spyglass : Constraints checking / CDC Checking
LEC / Formality : Formal Verification, VCLP.
Primetime : Zero delay Timing analysis.
Location:
IN-KA-Bangalore, India (eInfochips)
Time Type:
Full time
Job Category:
Engineering Services
📌 Senior Engineer Level 1 Pune
🏢 Arrow
📍 Pune
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