We are looking for a talented and experienced RTL Design Engineer to join our team and play a key role in the design and development of next-generation ASICs/SoCs. You will be responsible for all aspects of RTL design, from concept to RTL coding, verification, and integration.
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Responsibilities:
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- Develop RTL code for complex digital circuits using Hardware Description Languages (HDLs) such as Verilog or VHDL
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- Perform functional verification using simulation and formal methods
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- Participate in code reviews and ensure adherence to coding standards
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- Analyze timing performance and perform static timing analysis (STA)
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- Collaborate with design, verification, and synthesis teams to ensure successful tape-out
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- Stay up-to-date with the latest RTL design methodologies and tools
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Qualifications:
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- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
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- 5+ years of experience in RTL design for ASICs/SoCs
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- Proven experience in designing and verifying complex digital circuits
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- Proficiency in Verilog or VHDL
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- Experience with verification methodologies (e.g., UVM)
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- Strong understanding of digital design concepts (combinational logic, sequential logic, state machines)
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- Experience with SDC (Standard Delay Constraint) format for timing closure
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- Experience with scripting languages (e.g., Python, Perl) is a plus
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- Excellent communication, teamwork, and problem-solving skills
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Benefits:
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- Competitive salary and perks package
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- Opportunity to work on cutting-edge technologies
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- Collaborative and fast-paced work environment
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- Potential for professional growth and development
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