Job DescriptionWe're Hiring | Memory Layout Engineers
nWe're looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.
nExperience: 4+ Years
nLocation: Bangalore
nKey Responsibilities:
n
- n
- Design memory layouts for various building blocks, including:n
- Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocksn
- Integrate top-level memory layouts.n
- Perform physical verification using DRC and LVS.n
- Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.n
- Analyze layouts for power integrity and signal integrity.n
- Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.n
nRequired Skills:
nStrong hands-on experience in Memory Layout for advanced technology nodes.
nExpertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).
nSolid understanding of physical verification, layout methodologies, and semiconductor design flows.
nScripting knowledge is an added advantage.