Key Tasks / Responsibilities

- You will be part a Physical Design / Timing Closure team for projects with GHz freq range and cutting edge technologies.

- Hand on Understanding Synthesis & STA Experience on low power node technologies.

- Experience with sign- off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks

- Experience with full- chip static timing analysis through tapeout, gate level simulations.

- Experience with Power Analysis using Power Artist and PTPX

- Work Experience in Synthesis Constraints development, LINT checks, and CDC checks

Key skills / Background

- 5 to 8 years of Experience in Synthesis and STA

- Good understanding of overall design Flow RTL to GDS.

- Should have worked on several full chip designs both flat and hierarchical designs





- Knowledge on DFT and Physical design is preferred

- Expertise in STA tools and flow Synopsys/ Cadence tool experience is preferred

- Solid knowledge in RTL to Net list handoff to Physical design team Experience

- Experience with VHDL/Verilog

- Knowledge on Perl / TCL / Python scripting languages

Personal Skills

- Excellent communication and interpersonal skills

- Self motivated

- Take ownership of problems

- Creative problem solving

- Strong and effective presentation skills, able to operate at multiple levels including senior management

- Team player

📌 Sr. Logical Synthesis Engineer (India)
🏢 Chiplogic Technologies
📍 India