Responsibilities
Synthesis Tool Expertise: Proficiency in using and optimizing synthesis tools like Synopsys Design Compiler or Cadence Genus.
Constraints Development and Management: Developing and maintaining Synthesis Design Constraints (SDC) to meet performance, power, and area targets.
Optimization Techniques: Implementing various optimization techniques to improve performance, reduce power consumption, and minimize area. This includes clock gating, multi-voltage design, and power gating.
Timing Analysis: Performing timing analysis to identify and resolve timing violations, ensuring the design meets timing requirements.
Design Quality Checks: Performing design quality checks, including those for data quality, clock domain crossing, and redundant connections.
Collaboration:
Working closely with other engineers, including design, verification, and process engineers, to ensure successful design and product development.
Problem Solving: Troubleshooting and resolving design-related issues to ensure successful product development and release.
Documentation: Preparing and reviewing design documentation, including schematics, layouts, and test plans.
Scripting and Automation: Utilizing scripting languages (like Tcl, Perl, or Python) to automate synthesis tasks and improve efficiency.
Minimum
Qualifications:
Education: A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.