Location: Bengaluru

Experience: 4–10 years

Employment Type: Full time

About the Role

We are looking for SoC design engineers to own RTL integration and front-end signoff for complex SoCs. You will integrate IPs at subsystem and top level, and drive Lint, CDC, RDC, low-power (VCLP) and synthesis checks to closure for tapeout.

Key Responsibilities
SoC integration: Integrate IPs at subsystem and top level, including clock, reset, memory, pad/IO and interconnect. Build and maintain top-level RTL and connectivity.
Lint: Run Lint checks, analyze violations, drive fixes with IP owners, and manage waivers to signoff.
CDC/RDC: Set up constraints, and analyze synchronizers, reconvergence, glitches and reset domain crossings. Deliver clean signoff reports.
Low power (VCLP): Write and review UPF. Verify isolation, level shifters, retention and power switches using static low-power checks.
Synthesis: Write SDC constraints, run synthesis, and improve timing, area and power QoR. Run logic equivalence checks (RTL vs netlist).
Collaboration:



Work with verification, DFT, STA and physical design teams through tapeout.

Must-Have Skills
Robust Verilog/SystemVerilog RTL design and debug.
Hands-on experience with at least three of: Lint, CDC, RDC, VCLP/UPF, synthesis, SoC integration.
Good understanding of clocking, reset architecture and low-power design concepts.
SDC constraints and UPF knowledge.
Scripting in Tcl, Python or Perl, plus Makefile-based flows.

Positive to Have
Full-cycle tapeout experience.
ARM-based SoC and AMBA protocols (AXI/AHB/APB).
Exposure to DFT, STA (PrimeTime) or LEC flows.
Education: BE/BTech/ME/MTech in ECE, EEE, VLSI or a related field.
Screening keywords for TA: VC SpyGlass, SpyGlass Lint/CDC/RDC, Questa CDC, Meridian CDC/RDC, VC LP, VCLP, Conformal LP, UPF, CPF, Design Compiler, Fusion Compiler, Genus, Formality, Conformal LEC, SDC, SoC integration

📌 System On Chip Design Engineer Bengaluru (India)
🏢 Leadic Design
📍 India