Job DescriptionWe are looking for an experienced Senior ASIC RTL Design Engineer to join our growing semiconductor design team. The ideal candidate will have robust experience in RTL development, micro-architecture design, and SoC integration.
nLocation: Bangalore/Hyderabad
nExperience: 8–15 Years
nKey Responsibilities:
n
n
Design and develop synthesizable RTL using Verilog/System Verilogn
Translate architecture specifications into micro-architecture and RTL implementationn
Develop high-performance and low-power digital design blocksn
Work closely with verification teams for functional validation and debugn
Perform design reviews and ensure coding quality and design guidelinesn
Collaborate with physical design teams to meet timing, power, and area requirementsn
Debug RTL issues and support silicon bring-up when requiredn

nRequired Skills:
n
n
Solid expertise in Verilog and System Verilogn
Solid understanding of digital design fundamentals and computer architecturen
Experience with AMBA protocols such as AXI, AHB, and APBn




Knowledge of synthesis, timing closure, and low-power design techniquesn
Familiarity with simulation and debugging toolsn
Experience working in ASIC/SoC design environmentsn

nPreferred Qualifications:
n
n
Strong debugging and problem-solving skillsn
Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.n
Strong understanding of digital logic design principles.n

nAbout us:
nTessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an productive turnkey solution for silicon bring-up, spec to the product.
nWith 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with

📌 Lead/ Manager Rtl Design Karnataka
🏢 TESSOLVE
📍 Karnataka