19 Sep
|
Weekday AI
|
Hyderabad
19 Sep
Weekday AI
Hyderabad
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Experience: 2+ yrs
Location: Hyderabad, Telangana, India
Job Type: Full-time
As a Design Verification Engineer – GLS, you will work on gate-level and post-synthesis verification of complex digital designs. You will develop, configure, execute, and debug GLS environments while analysing functional and timing-related failures.
A key part of the role will involve SDF-annotated simulations, where you will investigate timing behaviour and failures across different design stages. You will work closely with RTL, synthesis, Static Timing Analysis (STA), Physical Design, DFT, and other engineering teams to identify the source of issues and drive them through resolution.
You will also contribute to full-chip and subsystem-level verification, execute regression suites, analyse failures, track coverage, and support overall verification closure. The role provides an chance to work on complex SoC/ASIC designs and contribute to improving verification methodologies, automation,
and debugging efficiency.
Requirements
Key Responsibilities
- Lead Gate-Level Simulation (GLS) and post-synthesis verification activities for complex SoC/ASIC designs.
- Develop, configure, execute, and debug gate-level simulation environments.
- Work extensively with SystemVerilog and UVM-based verification environments.
- Perform SDF-annotated timing simulations and analyse timing-related failures.
- Debug GLS failures across RTL, synthesized netlists, constraints, libraries, testbenches, and simulation configurations.
- Investigate functional, timing, reset, initialization, and X-propagation issues observed during gate-level simulation.
- Collaborate with RTL, Synthesis, STA, Physical Design, and DFT teams to identify and resolve root causes.
- Execute large-scale simulation and regression suites and analyse failures systematically.
- Track verification status, regression results, coverage,
📌 GLS verfication engineer (Hyderabad)
🏢 Weekday AI
📍 Hyderabad