Job Type: Full-time

Location:Noida, Uttar PradeshExperience:4+ YearsEmployment Type:Full-timeJob OverviewThe role involves development, optimization, and physical verification ofstandard cell librariesfor advanced semiconductor technologies. The engineer will work closely with circuit designers, characterization, library, physical design, and technology teams to deliver high-quality, PPA-optimized standard cells meeting stringentperformance, power, area, and manufacturabilityrequirements.Key ResponsibilitiesDesign and develop physical layouts forstandard cellsincluding combinational and sequential logic cells.Work on different standard cell variants such asNAND, NOR, INV, BUF, AOI/OAI, MUX, XOR/XNOR, Flip-Flops, Latches, Tie cells, Level Shifters and related library cells .Performfull-custom layoutof standard cells based on schematics and technology requirements.Optimize cell layouts forarea, timing, power, routability and overall PPA .Ensure proper cell architecture, device placement, diffusion sharing, pin accessibility and routing while maintaining design-rule compliance.PerformDRC, LVS, ERC and other physical verificationactivities and resolve violations.Work with circuit designers to understand electrical requirements and translate schematics into robust, manufacturable layouts.Analyze and resolve layout-related issues affectingtiming, power, leakage, parasitics and signal integrity .Support development and optimization of standard-cell libraries across differentprocess technologies and PVT conditions .Collaborate with characterization teams for timing,



power and functionality validation of standard cells.Supportcell benchmarking and PPA analysisagainst existing/reference libraries.Participate in library development activities from layout implementation through physical verification and release.Work closely with global teams across design, technology, characterization and physical design.Develop or use scripting/automation wherever applicable to improve layout and verification productivity.Required Skills & Experience4+ years of relevant experience in Standard Cell Layout / Library Development.Strong hands-on experience instandard cell physical layout .Good understanding ofCMOS circuits, transistor-level design and semiconductor device fundamentals .Strong knowledge of standard-cell architecture and layout techniques.Hands-on experience with:Cadence Virtuoso / Layout XLCalibre DRC/LVSor equivalent physical verification toolsStrong understanding of:DRC / LVS / ERCDesign-rule constraintsPPA optimizationDevice matching and layout-dependent effectsParasitics and their impact on circuit performancePin accessibility and routing considerationsExperience working withadvanced technology nodesis preferred.Good understanding of differentcombinational and sequential standard cells .Ability to debug physical verification issues independently.Good communication and cross-functional collaboration skills.Valuable to HaveExperience instandard-cell library development / characterization .Exposure toLiberty (.lib) generation and characterization flows .Knowledge of timing and power characterization using tools such asLiberate / SiliconSmart .Exposure toPrimeTime / STAor other timing-analysis tools.Understanding ofPVT corners, setup/hold, slew, load and timing arcs .Experience withFinFET / advanced-node technologies .Knowledge ofDTCO / library optimizationconcepts.Scripting experience inPython, Perl, TCL or SKILL .Exposure to digital implementation / RTL-to-GDS flow.Experience working with high-performance or low-power standard-cell libraries.Educational QualificationB.E./B.Tech/M.E./M.Tech inElectronics, Electrical Engineering, VLSI or a related discipline .

📌 Std Cell Layout Engineer (Mumbai)
🏢 leadIC Design
📍 Mumbai