We are seeking an experienced Senior CAD Engineer to develop, deployment, and support of advanced VLSI CAD methodologies and automation solutions. The role focuses on improving design productivity, quality, and scalability across RTL-to-GDS implementation flows. The ideal candidate will work closely with Physical Design, Frontend, DFT, STA, and EDA vendors to drive robust CAD infrastructure and enable successful tape-outs for complex SOCs.
Develop, and maintain scalable CAD flows for synthesis, physical design, STA, low-power verification, and signoff.
Collaborate with design, verification, DFT, and implementation teams to understand flow requirements and deployment challenges.
Debug complex flow, tool, and infrastructure-related issues across project execution.
Develop automation scripts, regression environments, dashboards, and flow monitoring infrastructure.
Mentor engineers and establish CAD best practices across teams.
Bachelor's or Master's degree in Electronics, Computer Engineering, VLSI, or related field.

- 5+ years of experience in CAD engineering, physical design methodology, or EDA flow development.
- Solid expertise in ASIC/SOC implementation flows including synthesis, P&R;, STA, physical verification, and low-power methodologies.
- Hands-on experience with industry-standard EDA tools such as Cadence, Synopsys, and Siemens EDA tool suites.
- Strong programming and scripting skills in Tcl, Python, Perl, and Shell scripting.
- Experience with distributed computing environments, regression frameworks, and infrastructure management.
- Experience with cloud-enabled EDA infrastructure and workload management systems.

Exposure to AI/ML-driven CAD optimization methodologies.
Delivery of stable, scalable,



and high-quality CAD flows adopted across multiple projects.
Fast resolution of tool and flow issues minimizing project execution risk.
Strong technical leadership, mentoring, and positive influence on engineering methodology.
Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package
TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.
The semiconductor industry is going through its biggest architectural shift in 40 years:
2nm and beyond delivers marginal performance gains. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.
No Politics, No Bureaucracy
There are no layers, no approval chains, no corporate theater.
If it works, we ship it.
No endless meetings, no PowerPoint presentations to convince middle management.
Remote-Friendly, Global Team
Building a world-class design center in Bangalore
Move Fast, Ship Real Products
We're not a research project. We're building to win.
This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
We don't care about titles or politics. Every hyperscaler needs what we're building.
We've built and exited semiconductor companies at scale. The traction is de-risked. You're building the silicon infrastructure that powers AI.

📌 Senior Computer Aided Design (CAD) Technician (Bengaluru)
🏢 tylsemi
📍 Bengaluru