At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Foundry PDK Design Enablement Engineer
Experience Level: 2-4 Years
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field
We are seeking a highly motivated Foundry Process Technology, PDK & DTCO Engineer with 2-4 years of experience to join our process technology group. In this role, you will bridge the gap between process technology and design, driving next-generation semiconductor technology through cutting-edge path-finding methodologies. The ideal candidate possesses a strong foundation in PDK enablement, physical verification decks, process/design interaction electrical studies, Spice model understanding and design automation.
Technology Study Activities: Conduct rigorous standard cell, SRAM, and custom circuit benchmarking alongside interconnect optimization to maximize power, performance, and area (PPA).




Design, develop, and maintain robust scripts and automated execution flows for PDK enablement/validation and PDK analysis.
Industry Experience: 2-4 years of hands-on experience in semiconductor technology analysis, foundry PDK enablement, and the co-optimization of PDK components like LVS, DRC, Parasitic Extraction, spice models. Robust understanding of PDK design enablement flows. Physical Verification & EDA: Deep knowledge of Layout Versus Schematic (LVS), Design Rule Checking (DRC), Parasitic Extractions, and Spice models at transistor level. Direct experience or high proficiency with Cadence-based tool suites is highly advantageous.
Proven experience interfacing with core PDK development teams, technology enablement units, or advanced technology benchmarking groups.

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