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Position:

Senior Engineer (Level 1)- Physical Design

Job Description:

Principal Accountabilities
Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
Execute block level place and route assignments from Netlist through GDS flow.
Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed.
Close STA timing across all corners and modes for blocks and should be able to generate ECO independently .
Work with design teams for closing CTS, IO timing, DFT timing.
Responsible for digital design automation,



flow-automation and regression across RTL-to-GDSII.

Job Complexity
Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below:
(1) Incumbent has knowledge and experience in own discipline and may still be acquiring higher level knowledge and skills. Incumbent builds knowledge of the organization, processes and customers, solves a range of straightforward problems, and analyzes possible solutions using standard procedures. A moderate level of guidance and direction is provided.
(2) Incumbent has extensive knowledge and experience in own discipline, possesses robust knowledge of the organization, processes and customers, solves a range of complex problems, and analyzes possible solutions using standard procedures. Limited guidance and direction is provided.

Experience / Education
Typically requires a 4 year degree and a minimum of 5 years of related experience; or an advanced degree without experience; or equivalent work experience.

Location:

IN-TG-Hyderabad, India-Gowra Palladium (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

📌 Senior Engineer Level 1 Physical Design Hyderabad (India)
🏢 Arrow Electronics
📍 India