Key Responsibilities
Leadership & Strategy: Build, mentor, and scale high-performing physical design and CAD teams across global sites.
Execution & Tape-out: Own full-chip and large block-level physical implementation, handling floorplanning, placement, clock tree synthesis (CTS), routing, and congestion analysis.
Signoff & Closure: Drive static timing analysis (STA), signal integrity, IR drop/electromigration (EM) closure, physical verification (DRC/LVS), and low-power verification (UPF/CPF).
Cross-functional Collaboration: Partner with architecture, RTL design, DFT, analog/mixed-signal, and packaging teams.
Methodology Innovation: Drive EDA tool optimization, advanced packaging/chiplet flows, and AI-driven automation frameworks.





Requirements

Requirements & Qualifications
Experience: 12–20 years in ASIC/SoC physical design and timing signoff, with at least 2+ years in a senior management or director role.
Education: B.Tech / M.Tech - Electronics / Electrical
Technical Mastery: Hands-on expertise with advanced technology nodes and EDA tools from vendors like Synopsys or Cadence.
Domain Knowledge: Deep understanding of low-power architectures (DVFS, power gating), multi-voltage domains, and high-speed interfaces.

📌 Sr Manager / Director Physical Design Bengaluru (India)
🏢 Recognized
📍 India