Job Description:

Job Description:
Architect and develop scalable and reusable Testbench setting using the framework of Verification Methodologies.
Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
Work with other members of the team, guide/mentor junior team members
Lead the documentation of verification strategy including Test plans, Verification Setting, pseudo-random tests, etc. Lead reviews with design/architecture.
Driver Verification quality and Efficiency improvements

Mandatory Requirements:




Bachelor’s degree in electrical/Electronics/Equivalent with 12+ years of relevant experience or Master’s degree in Electrical/Electronics/Equivalent with 10+ years of relevant experience
10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification leading a Core
Very proficient in System Verilog and Verification Methodologies like UVM/VMM
Good debug skills in analyzing regression failures and understanding of complex designs
A positive understanding of a complex protocol like PCI Express or other multi-layered protocol

These requirements are a plus:
Experience in PCIe protocol
Comfort with Makefiles
Experience with Verifying with other protocols like AXI

R027363

📌 Ic Verification Engineer Bengaluru (India)
🏢 Broadcom
📍 India