Hiring: Senior RTL Design Engineer – UCIe 2.0

Location: Bangalore, India

Experience: 5+ Years

We are looking for an experienced RTL Design Engineer with solid expertise in digital logic design, IP/SoC development, and hands-on experience with the UCIe 2.0 protocol.

If you have a solid foundation in RTL design and experience in RTL quality checks, including Lint, CDC, and RDC, we would love to connect with you!

Key Responsibilities
Design, develop, and optimize synthesizable RTL for IP and SoC blocks.
Work on digital logic design and implementation aligned with UCIe 2.0 protocol requirements.
Perform RTL quality checks, including Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis.
Collaborate with architecture, verification, synthesis, and SoC integration teams.
Support RTL debugging, design reviews, and quality improvements.
Contribute to equivalence checking and synthesis activities.




Support SoC RTL integration and resolve integration-related issues.

Required Skills & Experience
5+ years of hands-on experience in RTL design.
Solid experience in digital logic design for IP or SoC block development.
Mandatory hands-on experience with the UCIe 2.0 protocol.
Practical experience with RTL quality checks, including Lint, CDC, and RDC.
Proficiency in Verilog/SystemVerilog and RTL design methodologies.

Good to Have
Experience with RTL equivalence checking and formal verification.
Knowledge of synthesis flows and timing-driven RTL optimization.
Experience in SoC RTL integration and subsystem-level integration.
Familiarity with semiconductor design flows and ASIC development.

📌 Rtl Design Engineer – Ucie 2 0 Bengaluru
🏢 LanceSoft
📍 Bengaluru