About the job Job: Physical Design Engineer Location: Bengaluru | Noida Employment Type: Full-time Experience: Senior-level Function: Semiconductor Engineering — Physical Design About SiliconBoard SiliconBoard connects semiconductor engineering talent with companies across the semiconductor ecosystem. This opportunity is offered through the SiliconBoard Talent Network. Shortlisted profiles are evaluated and shared with hiring companies within our partner network for relevant open positions. About the Role We are looking for experienced Physical Design Engineers with strong hands-on experience in ASIC physical implementation and design closure. You will work across the physical design flow — from floorplanning and placement through clock tree synthesis, routing, timing closure, and sign-off. The role involves working closely with RTL, STA, DFT, power, verification, and implementation teams to meet power, performance, area, timing, and manufacturability targets. Key Responsibilities Physical Design Planning - Understand design specifications, architecture, constraints, and implementation requirements. - Define the physical implementation strategy based on block size, timing, power, area, and routing constraints. - Work with RTL, architecture, STA, and implementation teams to plan design closure. - Identify early physical design risks and drive mitigation plans. Floorplanning - Develop block-level and chip-level floorplans. - Plan macro placement, standard-cell regions, blockages, and physical constraints. - Optimize floorplans for timing, routability, congestion, and power. - Work on pin placement and interface planning. - Identify and resolve congestion and floorplan-related implementation issues. Power Planning - Develop and implement power distribution strategies. - Plan power rings, straps, grids,



and supply connectivity. - Support IR-drop and electromigration analysis. - Work with power and reliability teams to ensure robust power delivery. Placement and Optimization - Perform standard-cell placement and optimization. - Analyze timing, congestion, utilization, and power during implementation. - Optimize the design to improve PPA while maintaining design quality. - Debug implementation issues and improve physical convergence. Clock Tree Synthesis - Implement and optimize clock distribution networks. - Control skew, latency, transition, insertion delay, and clock balance. - Analyze and resolve clock-related setup and hold issues. - Debug CTS and post-CTS implementation problems. - Support clock-tree optimization for power and timing. Routing and Post-Route Optimization - Perform global and detailed routing. - Analyze routing congestion, DRC issues, and signal-integrity concerns. - Optimize post-route timing, power, and design quality. - Work on routing-related fixes and engineering change orders where required. Timing Closure - Analyze setup and hold violations across implementation stages. - Work closely with STA and RTL teams to resolve timing issues. - Support timing ECOs and design optimization. - Drive timing convergence across multiple modes and corners. Physical Verification and Sign-off - Support DRC, LVS, antenna, density, and physical sign-off checks. - Work on IR-drop, electromigration,



signal integrity, and reliability analysis. - Resolve implementation and sign-off violations. - Support final design closure and tapeout readiness. Required Qualifications - B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline. - Robust hands-on industry experience in ASIC Physical Design. - Experience with floorplanning, placement, CTS, routing, and timing closure. - Good understanding of power, performance, and area trade-offs. - Hands-on experience with congestion analysis and implementation optimization. - Understanding of static timing concepts, setup/hold analysis, and timing constraints. - Experience working with multi-mode, multi-corner design scenarios. - Positive understanding of digital design and ASIC implementation fundamentals. - Strong debugging and physical implementation skills. - Experience taking blocks or designs through significant stages of the physical design flow. Preferred Qualifications Relevant experience in one or more of the following areas: - Block-level physical design - SoC physical implementation - Floorplanning - Macro placement - Pin placement - Power planning - Placement optimization - Clock Tree Synthesis - Routing - Static Timing Analysis - Setup and hold closure - Congestion analysis - Timing ECOs - PPA optimization - IR-drop analysis - Electromigration analysis - Signal integrity - Physical verification - DRC / LVS - Design sign-off - ECO implementation - Tapeout Experience in the following areas is also preferred: - Advanced process nodes - High-frequency designs - Low-power implementation - Large and complex blocks - Multi-voltage designs - Hierarchical physical design - Multiple successfu

📌 Physical Design 6-18 Years Semiconductors (Bengaluru)
🏢 SiliconBoard
📍 Bengaluru