Job Description: JD for Scan/ATPG engineer:

Summary: Scan insertion experience using Fusion compiler. Familiar with ATPG and ATPG simulations

Experience and understanding of ASIC DFX, Scan synthesis, Integration flow using Fusion Compiler, ATPG experience in tile and SoC level experience. Applicant should be familiar with scan hardware compressions, failure mechanisms and debug processes.
Familiar in ICL Extraction, SSN, IJTAG,EDT, Test Kompress, simulation and verification flow and experience of working in DFX architecture of complex SOC. Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem Experience in End-to-End DFX flow development/creation. DC/AC scan (at-speed) development, debug and test. Expert in at least one of the scripting tool (Perl, Python, TCL)



and ability to create complex flows/scripts that provide scalable solutions to DFX implementation.

Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, Synopsys - Fusion compiler, Design Compiler. Scan/ATPG patterns & test flows development, EDT, SSN and SSH architecture understanding, IJTAG,EDT, Test Kompress, simulation and verification flow and experience of working in DFX architecture of complex SOC Patterns re-targeting

Valuable if any AMD/Intel/Qualcomm experience

This is the requirement for CAD, FLOW and METHODOLOGY team. Hence strict requirement on scripting is required along with core skills.

Please filter them at your side, conduct mock interview at your end if they are good in scripting.

📌 Engineering - Verification Engineer 4 (India)
🏢 Objectwin Technology India
📍 India