We are looking for on-chip SoC Interconnect micro-architect and design lead for chiplet based high-performance Compute and AI silicon development.
Specify the data-path fabric for the high-bandwidth routes: bandwidth provisioning, pipeline depth, buffering strategy, and back-pressure propagation between major subsystems.
Define the arbitration and QoS policy for shared fabric resources: priority assignment per traffic class, bandwidth reservation, and starvation-prevention mechanisms.
Own or closely review all fabric RTL: bus bridges, async FIFOs, arbiters, address decoders, and pipeline registers that form the on-chip interconnect.
Drive integration assembly: own the top-level connectivity netlist that instantiates all major blocks and wires them through the fabric, serving as the integration point of truth.
Define and own the fabric performance model: estimate bandwidth utilization per path under representative traffic mixes for each operating mode and identify bottlenecks.
Establish fabric-level bring-up tests: register accessibility checks, path connectivity tests, and loopback sequences that confirm the interconnect is healthy before full subsystem integration testing begins.
Coordinate with the physical design team on fabric floorplan implications: block placement driven by dominant data flow, clock-region boundaries, and wire-length budgets for timing closure.
BS/MS in Electrical Engineering, Computer Engineering, or equivalent with 12+ years of digital IC design, with at least 4 years owning on-chip interconnect, bus fabric, or NoC architecture at block-lead or integration-lead level.




able to write and review bus bridge RTL and understand ordering rules, response channels, and error signaling.
Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC).
Familiarity with AMBA CHI or ACE coherency extensions and their impact on fabric design.
Solid understanding of CDC design: async FIFO design, gray-code counters, synchronizer topologies, and CDC verification methodology.
Experience owning the top-level integration netlist or chip-level assembly RTL on a multi-block design.
Strong SystemVerilog skills: arbiters, FIFOs, pipelines, address decoders, and parameterized bus infrastructure.
Experience with static timing constraints for multi-clock designs
Background with high-speed chiplet or SoC integration at advanced nodes (7 nm or below), including floorplan-driven bus topology decisions.
Experience building or maintaining an automated register-map generation flow (SystemRDL, IP-XACT, or similar).
Prior role as chip-level integration lead responsible for assembling subsystem IPs into a complete design.
Experience with formal property verification of bus protocols or CDC crossings.
Hybrid/On-site - Bangalore,



Remote - India
Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package
TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.
The semiconductor industry is going through its biggest architectural shift in 40 years:
2nm and beyond delivers marginal performance gains. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.
No Politics, No Bureaucracy
There are no layers, no approval chains, no corporate theater.
If it works, we ship it.
No endless meetings, no PowerPoint presentations to convince middle management.
Remote-Friendly, Global Team
Building a world-class design center in Bangalore
Move Rapid, Ship Real Products
We're not a research project. We're building to win.
This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
We don't care about titles or politics. Every hyperscaler needs what we're building.
We've built and exited semiconductor companies at scale. The traction is de-risked. You're building the silicon infrastructure that powers AI.

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