Role overview Own the architecture and technical execution of analog IP blocks used in Gate Drivers, DC-DC Converter and Intelligent Power-management Platforms. Define the “what” and “why” of each analog IP block and guide junior analog IC design engineers on implementation. Responsibilities
• Behavioural modelling and architecture translation: Work with the Principal Power Architect to translate product architecture into system-level behavioural models covering functional behaviour, key performance parameters, interfaces, operating modes and critical corner cases before transistor-level implementation.
• System-level trade-offs: Evaluate performance, efficiency, speed, accuracy, power, area, noise, reliability, complexity and cost. Use system simulations to identify where performance must be optimized and where specifications can be relaxed.
• IP specification derivation: Convert product requirements into realistic, optimized block-level specifications; identify dependencies and allocate system-level error and performance budgets across IP blocks.
• IP architecture and technical direction: Guide junior engineers in choosing circuit architectures and implementation approaches; challenge conventional solutions, compare alternatives and make performance, power, area and robustness trade-offs.
• IP integration and subsystem ownership: Integrate analog IP blocks into functional subsystems, define interfaces and operating dependencies, and ensure the blocks work correctly together.
• Subsystem modelling and verification: Maintain behavioural and mixed-level simulations covering startup, shutdown, transients, loading, feedback, protection, noise, timing and worst-case conditions beyond block-level simulations.
• Quality and sign-off: Establish standardized design and sign-off checklists covering specifications, PVT, Monte Carlo, mismatch, startup, stability, noise, reliability, interfaces, loading, post-layout behaviour, corner cases and known limitations.



Ensure each IP meets the agreed quality bar before integration.
• Technical review and mentoring: Review junior engineers’ architectures, specifications, simulations and sign-off work; identify problems early, strengthen technical judgment and develop independent IP ownership.
• Innovation and circuit excellence: Pursue new circuit techniques, performance improvements, area and power reductions, robustness and differentiated features; turn ideas into measurable experiments and silicon-relevant improvements.
• Analog-digital integration: Own control and status interfaces, timing, clocking, resets, power sequencing, programmability, trimming, calibration, protection and fault handling, and digital control of analog functions. Align analog and digital assumptions at subsystem level.
• Silicon readiness and debug: Lead subsystem silicon readiness and debug, correlate measurements with simulation, drive root-cause analysis and feed learning into specifications, models, architectures and checklists.
• Reusable IP and methodology: Define standard interfaces, modelling conventions, verification methods, design reviews and sign-off criteria. Develop documented, silicon-proven IP and a scalable library for future Gate Driver and DC-DC products. Required Qualifications
• 10–15 years of relevant analog, mixed-signal or power IC design experience, including 10+ years of silicon-proven Analog/Mixed-Signal/Power IC expertise and hands-on ownership of complex analog blocks.
• Architecture and system thinking: Translate system requirements into optimized IP specifications and behavioural models, working closely with architects and making circuit




- and system-level trade-offs.
• Strong understanding of MOSFET/device physics and BCD/HV-CMOS technologies.
• Hands-on simulation and verification using DC, AC, transient and noise analysis; PVT, mismatch, Monte Carlo, corner analysis, stability and reliability.
• Technical leadership: Lead a team, establish design methodologies, review architectures and designs, challenge assumptions constructively and make decisions using data and engineering judgment.
• People leadership: Mentor engineers into independent analog IP owners, delegate effectively, build accountability and develop a high-performance engineering culture.
• First-principles problem solving and demonstrated innovation in architectures, circuits and techniques.
• Cross-functional collaboration with architecture, layout, verification, digital, applications, product/test, process technology and customers to resolve system-level issues.
• Robust proficiency in Cadence Virtuoso, Spectre/Spectre X, ADE Explorer/Assembler, HSPICE, Verilog-A/AMS and Calibre DRC/LVS/PEX.
• Familiarity with MATLAB/Simulink, Python, Verilog/SystemVerilog and automated simulation/regression flows.
• M.
S./M.
Tech./Ph.
D. in Electrical/Electronics Engineering, Microelectronics or VLSI Design. Preferred Qualifications
• Understanding of GaN, SiC and IGBT devices and their implications for circuit design. Behavioral competencies
• Ownership mindset: Own development from system architecture, behavioural modelling and transistor-level design through verification, layout, sign-off, silicon bring-up, debug and root-cause analysis; raise issues early, drive them to closure and remain accountable through silicon/product qualification.
• Emotional intelligence: Demonstrate self-awareness, empathy and interpersonal judgment; give candid feedback, listen to opposing views, handle disagreements constructively and maintain trust under schedule and technical pressure.

📌 Staff Analog/Power IC Design Engineer – Design Lead (Bengaluru)
🏢 IndiRFTech.com
📍 Bengaluru