Verification Leadership: Drive the verification of mixed-signal ICs using best practices to ensure first-pass silicon success
Model Creation: Create and verify block-level models (e.g., System Verilog, VAMS) for use in top-level mixed-mode simulations
Test Development: Develop application-specific test benches with automated checkers to evaluate IC functionality and robustness
Collaboration: Work closely with application, analog design, and digital design leads to verify system-level and IC-level functions
Debug Support: Partner with the design team to analyze and address errors found during the verification process
Team Culture: Foster a cooperative, cutting-edge, and resilient team culture that encourages open communication
Qualifications
Education: Graduate with a Bachelors or Master’s degree in Electrical Engineering or a related field
Design Knowledge:
Experience in analog or mixed-signal design verification, with proficiency in UVM-based methodologies
Technical Expertise: Skilled in modeling analog mixed-signal blocks such as bandgap, oscillators, ADCs, DACs, LDOs, SerDES, DDR, GPIO.
Tool Knowledge: Hands on experience on AMS verification Tools (Synopsys XA, Cadence DiscoveryAMS)
EDA Tools: Knowledge of common tools like Cadence Virtuoso, Maestro, and vManager
Scripting Skills: Proficiency in System Verilog, VAMS, or real-number modeling for designing and simulating verification models
Soft Skills: Solid communication and leadership abilities, with the ability to persevere through challenges and drive root-cause analysis to closure