Key Skills
Full-Chip Physical Verification (PV) signoff with lower tech nide and TSMC Foundry
Expertise in Calibre / Pegasus Physical Verification flow
LVS, DRC, ERC, Antenna, Density and Reliability checks
Experience with large hierarchical SoCs and top-level integration
Robust debugging of physical verification violations and signoff issues
Valuable understanding of advanced technology nodes (3/4nm) and foundry rule decks
Coordination with Physical Design, Layout, and STA teams
Requirements
Hands-on experience driving full-chip PV signoff for complex SoCs.
Robust understanding of layout verification methodologies and tapeout flows.
Ability to independently debug and resolve DRC/LVS/ERC violations.
Experience handling top-level signoff and tapeout activities.
Preferred
Experience with Cadence Innovus implementation flow.
Scripting knowledge (Perl/Python/TCL).
📌 Physical Verification Lead Chennai
🏢 LanceSoft
📍 Chennai
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