Job Description
Mandatory skills
- P&R;, timing, power/voltage analysis, and leadership.
Physical Design experience with 3+ years of experience in ASIC/SoC Physical Design. Candidate should have robust hands-on expertise in Cadence Innovus, Synopsys Fusion Compiler, and Primetime, with experience in timing closure, PPA optimization, physical implementation, and signoff. Experience with Voltage/IR-drop and power integrity analysis tools is required. Responsibilities
• Physical Design experience with 3+ years of experience in ASIC/SoC Physical Design.
• Candidate should have strong hands-on expertise in Cadence Innovus, Synopsys Fusion Compiler, and Primetime, with experience in timing closure, PPA optimization, physical implementation, and signoff.
• Experience with Voltage/IR-drop and power integrity analysis tools is required. Required Skills
• Mandatory skills
- P&R;, timing, power/voltage analysis, and leadership.