SRAM Layout OS Engineer (2-5 yrs) Design and optimize SRAM layouts ensuring DRC/LVS compliance, yield optimization, and performance across advanced process nodes.
- Design, develop, and optimize SRAM memory layouts for advanced semiconductor process nodes, ensuring high performance, low power consumption, and area efficiency while meeting stringent design specifications and technology constraints.
- Collaborate closely with circuit design, process integration, and verification teams to translate schematic requirements into robust physical layouts, addressing design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC).
- Perform layout optimization for yield, reliability,
and manufacturability by applying best practices for matching, symmetry, shielding, and minimizing parasitics, while resolving complex layout-related issues across multiple SRAM architectures.
- Support silicon validation and debug activities by analyzing post-silicon data, identifying layout-related root causes of failures, and implementing corrective actions to improve future design revisions and production readiness.
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