Job Overview

We are looking for a Physical Design Engineer with 1 to 2 years of hands-on experience in block-level or sub-chip physical implementation. In this role, you will work closely with senior technical leads, synthesis, STA, and physical verification teams to execute Netlist-to-GDSII design flows. You will be responsible for driving design implementation across placement, routing, clock tree synthesis, and timing closure for contemporary ASIC/SoC designs.

Key Responsibilities

- Floorplanning & Power Planning:

Assist in block-level floorplanning, pin assignment, macro placement, and constructing low-IR drop power delivery networks (PDNs).

- Placement & CTS:

Run netlist placement, optimize logic structures, and execute Clock Tree Synthesis (CTS) to achieve minimal skew and latency targets.

- Routing & Optimization:

Perform detailed global/track routing,



resolving congestion issues and crosstalk noise while optimizing Power, Performance, and Area (PPA).

- Static Timing Analysis (STA):

Conduct STA using PrimeTime/Tempus, trace setup/hold violation paths, and implement ECO fixes across multi-mode multi-corner (MMMC) conditions.

- Physical Verification:

Debug and resolve DRC, LVS, ERC, and Antenna checks to ensure clean physical layouts.

- Power Analysis:

Assist senior engineers with EM/IR drop analysis (static and dynamic) and implement power-aware fixes.

- Automation:

Write and maintain Tcl, Python, or Shell scripts to automate flow execution and custom data parsing in Linux environments.

Location: Bengaluru

Notice Period: Immediate

📌 Physical Design Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru