Looking for an experienced engineer with solid knowledge of SerDes and/or DDR circuit design in advanced technology nodes, including FinFET. Must have good understanding of STA concepts and hands-on exposure to Cadence Virtuoso.
Key Responsibilities
Design and analyze high-speed SerDes and/or DDR circuits.
Perform functional analysis, Static Timing Analysis (STA), and electrical sign-off.
Analyze the impact of process variations on circuit performance.
Evaluate power-performance trade-offs in high-speed SerDes designs.
Execute circuit design activities using AMD tools and support project execution.
Release PHYs for SoC integration.
Mandatory Skills
Robust understanding of SerDes domain and circuit design.
Positive knowledge of Static Timing Analysis (STA) concepts.
Hands-on exposure to Cadence Virtuoso.