Job Description: Senior Design Lead -Analog Layout Design
Experience
7 – 10 years of relevant industry experience in Analog/Mixed-Signal Layout Design.
Experience in one or more of the following domains:
Power Management
Data Converters
High-Speed Analog
IO Layout
Clocking Solutions
Custom IP Development.
Key Responsibilities
Key Responsibilities
Design high-quality, schematic-driven physical layouts for analog, mixed-signal, and custom digital blocks (e.g., PLLs, ADCs, DACs, LDOs, and PHY IPs).
Lead a team senior/junior layout design engineer, ensuring delivery excellence.
Drive execution and debugging of DRC, LVS, ERC, Antenna, and EMIR checks to ensure silicon-proven compliance.
Lead layout reviews, estimate schedules, and delegate sub-block tasks. Mentor junior/mid-level layout engineers and enforce design best practices.
Work closely with circuit designers, DFM (Design for Manufacturing) experts, and global engineering teams to optimize Power, Performance, and Area (PPA).
Evaluate recent EDA tools,
develop automation scripts (Skill/Perl/Python), and optimize layout methodologies to improve overall productivity.
Process Nodes Experience
Hands-on experience in one or more of the following technologies is preferred:
Intel Advanced Nodes
TSMC N16 / N7 / N5 / N3
Samsung Advanced Process Nodes
Global Foundries Technologies
Any BCD or Bi-CMOS process nodes.
Skill Requirements
Scripting
Basic programming or scripting skills in one of the below programming languages is highly preferred
SKILL / SHELL / PERL / TCL