Experience: 6+ Years | Location: Noida / Bangalore / Remote

Own block-level physical design implementation with a strong focus on timing closure, driving convergence across PPA and sign-off.

Key Responsibilities
Own end-to-end physical design of assigned blocks (floorplan route sign-off)
Drive timing closure across MMMC scenarios with deep analysis and debugging
Perform detailed STA (setup/hold, SI, OCV/derates) and ensure sign-off quality
Develop and validate timing constraints (SDC) with high coverage and accuracy
Work closely with STA/Sign-off teams to ensure correlation and closure
Identify and resolve critical timing bottlenecks, congestion, and SI issue
Execute ECOs for timing, power, and area convergence
Perform physical verification (DRC/LVS/Antenna) and ensure clean sign-off
Analyze IR/EM and support PDN optimization
Contribute to flow improvements and automation

Skills Required
Solid hands-on experience in PD tools (Innovus / ICC2 / Fusion Compiler)
Robust STA expertise using PrimeTime / Tempus (must-have)




Deep understanding of:
Timing closure techniques (setup/hold fixing strategies)
MMMC analysis and corner/mode interactions
OCV/AOCV/POCV, SI/crosstalk effects
Constraint development and validation (SDC)
Ability to debug complex timing issues beyond tool reports
Solid understanding of full PD flow (floorplan CTS routing sign-off)
Robust scripting skills (Tcl required; Python/Perl preferred)

Preferred
Experience at advanced nodes (16nm / 7nm / 5nm)
Experience handling high-frequency or timing-critical blocks

Soft Skills
Ability to independently own and close blocks under tight timelines

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Sr Pd Engineer Bengaluru
🏢 Tecquire Solutions
📍 Bengaluru